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This talk will show how some numerical issues can be (manually) detected and resolved, review benchmarks for AI/ML compact models and parameter extraction, and speculate on avenues for future improvements.\u003C/p>","2024-12-18T17:24:57.644Z","2025-03-02T21:19:22.922Z","2024-12-18T17:24:58.738Z","31",[804],{"id":135,"name":805,"committee":16,"position":16,"affiliation":806,"email":16,"biography":807,"createdAt":808,"updatedAt":809,"url_path_id":810,"contactPhoto":811,"socialLinks":845,"url_path":846},"Colin McAndrew","IEEE Life Fellow, NXP Fellow (retired), ECpE, Iowa State University","\u003Cp style=\"text-align:justify;\">Colin McAndrew (IEEE Life Fellow) received a B.E. degree (Hons.) in electrical engineering from Monash University, Melbourne, VIC, Australia, and a Ph.D. degree in systems design engineering from the University of Waterloo, Waterloo, ON, Canada. He worked at AT&T Bell Laboratories for 7 years, then for 29 years at NXP / Freescale / Motorola (retiring in 2024 as an NXP Fellow). He is now an Affiliate Full Professor in the department of electrical and computer engineering at Iowa State University. He has over 150 publications (22 invited, 4 best paper), was an editor of IEEE TED for 9 years and IEEE JEDS for 9 years, has been on conference committees for IEEE BCTM, CICC, ICMTS, and BMAS, and received the SRC Mahboob Khan Outstanding Mentor Award. He chaired the IEEE EDS committee on compact modeling from 2013 through 2016.\u003C/p>","2024-12-18T17:23:20.388Z","2025-03-02T21:18:51.352Z","26",{"id":812,"name":813,"alternativeText":16,"caption":16,"width":814,"height":815,"formats":816,"hash":841,"ext":341,"mime":344,"size":842,"url":843,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":844,"updatedAt":844},31,"mcandrew_photo.jpg",4037,3256,{"large":817,"small":823,"medium":829,"thumbnail":835},{"ext":341,"url":818,"hash":819,"mime":344,"name":820,"path":16,"size":821,"width":347,"height":822},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/large_mcandrew_photo_4c23fb1467.jpg","large_mcandrew_photo_4c23fb1467","large_mcandrew_photo.jpg",85.3,807,{"ext":341,"url":824,"hash":825,"mime":344,"name":826,"path":16,"size":827,"width":354,"height":828},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_mcandrew_photo_4c23fb1467.jpg","small_mcandrew_photo_4c23fb1467","small_mcandrew_photo.jpg",24.49,403,{"ext":341,"url":830,"hash":831,"mime":344,"name":832,"path":16,"size":833,"width":361,"height":834},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/medium_mcandrew_photo_4c23fb1467.jpg","medium_mcandrew_photo_4c23fb1467","medium_mcandrew_photo.jpg",49.67,605,{"ext":341,"url":836,"hash":837,"mime":344,"name":838,"path":16,"size":839,"width":840,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_mcandrew_photo_4c23fb1467.jpg","thumbnail_mcandrew_photo_4c23fb1467","thumbnail_mcandrew_photo.jpg",5.11,193,"mcandrew_photo_4c23fb1467",1448.1,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/mcandrew_photo_4c23fb1467.jpg","2024-12-20T13:18:18.461Z",[],"-12","-17",{"id":5,"session":849},{"id":5,"title":850,"teaser":67,"body":851,"createdAt":852,"updatedAt":853,"publishedAt":854,"url_path_id":855,"contacts":856,"url_path":884},"A CMC Origin Story and Some Thoughts about Future Sequels","\u003Cp style=\"text-align:justify;\">Dr. Green will reflect on the early days of the CMC, from its origin as a Sematech Workshop in 1995 to its rapid establishment as the premier, international modeling standards organization. He will share some of the challenges and accomplishments that were part of the journey, and he will highlight aspects of the CMC that make it a special and unique community for its members.\u003Cbr>\u003Cbr>Looking forward, Dr. Green will present some interesting technical challenges the CMC might want to consider for future standards. These are potential opportunities for the CMC to expand its portfolio, its membership and its influence. Specifically, three areas will be discussed: mechanical stress effects in semiconductor devices (e.g., due to chip-package interactions), the impact of X-Ray radiation, and integrated sensors. \u003C/p>","2024-12-18T17:24:29.519Z","2025-03-02T21:20:36.806Z","2024-12-18T17:24:30.792Z","30",[857],{"id":236,"name":858,"committee":16,"position":859,"affiliation":860,"email":16,"biography":861,"createdAt":862,"updatedAt":863,"url_path_id":864,"contactPhoto":865,"socialLinks":882,"url_path":883},"Keith Green","Distinguished Member of the Technical Staff","Texas Instruments & Distinguished Member of the Technical Staff (retired)","\u003Cp style=\"text-align:justify;\">Dr. Keith Green retired as a Distinguished Member of the Technical Staff at Texas Instruments in Dallas, Texas. During his 31 years with TI he provided technical leadership in the fields of semiconductor modeling, reliability and technology development. Presently, he works in TI’s Advanced Technology Development department and is responsible for integrated magnetic field sensor technologies.\u003C/p>\u003Cp style=\"text-align:justify;\">Dr. Green was a founder of the Compact Model Council consortium in 1996. He served as an officer from 2004 to 2015, including as Chairman from 2012 to 2015. Concurrently, he guided strategic university research as Chairman of the Semiconductor Research Corporation’s Compact Modeling Technical Advisory Board from 2004 to 2011. He has served on the board of Silicon Integration Initiative since 2015.\u003C/p>\u003Cp style=\"text-align:justify;\">Dr. Green has 25 patents, over 20 publications, and has been an invited speaker at several conferences and universities. He received Ph.D. and M.S. degrees in Electrical Engineering from the University of Florida and a B.S. degree in Electrical Engineering from the University of Delaware.\u003C/p>","2024-12-18T17:23:11.806Z","2025-06-18T21:53:40.586Z","25",{"id":107,"name":866,"alternativeText":16,"caption":16,"width":361,"height":361,"formats":867,"hash":878,"ext":341,"mime":344,"size":879,"url":880,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":881,"updatedAt":881},"Keith_Green_Photo_1bd9b31ed7 2.jpg",{"small":868,"thumbnail":873},{"ext":341,"url":869,"hash":870,"mime":344,"name":871,"path":16,"size":872,"width":354,"height":354},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_Keith_Green_Photo_1bd9b31ed7_2_2142f08348.jpg","small_Keith_Green_Photo_1bd9b31ed7_2_2142f08348","small_Keith_Green_Photo_1bd9b31ed7 2.jpg",30.04,{"ext":341,"url":874,"hash":875,"mime":344,"name":876,"path":16,"size":877,"width":26,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_Keith_Green_Photo_1bd9b31ed7_2_2142f08348.jpg","thumbnail_Keith_Green_Photo_1bd9b31ed7_2_2142f08348","thumbnail_Keith_Green_Photo_1bd9b31ed7 2.jpg",4.27,"Keith_Green_Photo_1bd9b31ed7_2_2142f08348",57.59,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/Keith_Green_Photo_1bd9b31ed7_2_2142f08348.jpg","2025-06-18T21:53:37.323Z",[],"-11","-16",{"id":243,"session":886},{"id":137,"title":887,"teaser":67,"body":888,"createdAt":889,"updatedAt":890,"publishedAt":891,"url_path_id":892,"contacts":893,"url_path":929},"Will Neural Networks Power the Next Generation Compact Models?","\u003Cp style=\"text-align:justify;\">‘Neural networks have taken the world by storm’ -- the saying goes currently. Neural network models are finding new applications every day, upending conventional workflow and ushering unprecedented productivity. Will they also power the next generation compact models? In this presentation, I will examine this possibility with some concrete examples. In essence, neural networks could learn patterns from same type of calculations, potentially providing results without having to go through those same calculation steps again and again. If this can indeed be achieved, it should substantially improve the speed of execution. Based on the recent work in the BSIM group, I shall discuss how neural networks perform in the context of reproducing conventional device level parameters such as current, voltage, noise etc. as well how it behaves in prototypical circuit simulation. Model development, usage of parameters and acceleration behavior will be presented. I shall also discuss potential outlook for such Neural Network enhanced compact models for advanced technology simulation.\u003C/p>","2024-12-18T17:25:18.409Z","2025-04-08T12:55:09.521Z","2024-12-18T17:25:20.999Z","32",[894],{"id":205,"name":895,"committee":16,"position":896,"affiliation":897,"email":16,"biography":898,"createdAt":899,"updatedAt":900,"url_path_id":901,"contactPhoto":902,"socialLinks":927,"url_path":928},"Sayeef Salahuddin","TSMC Distinguished Professor and IEEE, APS and AAAS Fellow","EECS, University of California, Berkeley","\u003Cp style=\"text-align:justify;\">S. Salahuddin is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. His work has mainly focused on exploring physics phenomena for energy efficient electronic devices.  Specifically, his work on negative capacitance in ferroelectric materials led to enhanced capacitance that is used in Industry's DRAM and back-end MIM capacitors. Salahuddin received the Presidential Early Career Award for Scientist and Engineers (PECASE). In addition, he received the IEEE Andrew S Grove Award, a technical field award given by IEEE for ‘For outstanding contributions to solid-state devices and technology’.\u003C/p>","2025-01-13T21:11:19.184Z","2025-06-18T21:54:29.177Z","48",{"id":903,"name":904,"alternativeText":16,"caption":16,"width":905,"height":905,"formats":906,"hash":923,"ext":908,"mime":344,"size":924,"url":925,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":926,"updatedAt":926},62,"salahuddin.jpeg",896,{"small":907,"medium":913,"thumbnail":918},{"ext":908,"url":909,"hash":910,"mime":344,"name":911,"path":16,"size":912,"width":354,"height":354},".jpeg","https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_salahuddin_a803a35a4b.jpeg","small_salahuddin_a803a35a4b","small_salahuddin.jpeg",31.74,{"ext":908,"url":914,"hash":915,"mime":344,"name":916,"path":16,"size":917,"width":361,"height":361},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/medium_salahuddin_a803a35a4b.jpeg","medium_salahuddin_a803a35a4b","medium_salahuddin.jpeg",59.76,{"ext":908,"url":919,"hash":920,"mime":344,"name":921,"path":16,"size":922,"width":26,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_salahuddin_a803a35a4b.jpeg","thumbnail_salahuddin_a803a35a4b","thumbnail_salahuddin.jpeg",4.87,"salahuddin_a803a35a4b",78.67,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/salahuddin_a803a35a4b.jpeg","2025-06-18T21:54:27.017Z",[],"-32","-18",{"id":63,"groupTitle":931,"sessions":932},"Invited Presentations ",[933,985,1025,1059,1106,1160,1193],{"id":14,"session":934},{"id":14,"title":935,"teaser":67,"body":936,"createdAt":937,"updatedAt":938,"publishedAt":939,"url_path_id":940,"contacts":941,"url_path":984},"Advancing Standard BSIM-BULK for Cryo-CMOS Applications","\u003Cp style=\"text-align:justify;\">This article explores a detailed analysis of an industry-standard model optimized for temperature scalability, ranging from room temperature to cryogenic temperatures. As the fundamental device physics of silicon is temperature-dependent, therefore, the electrical characteristics of field effect transistors (FETs) also exhibit noticeable changes with varying temperatures. One of the most prominent observations is the significant increase in the drain current as temperature decreases. This increase is primarily attributed to enhanced carrier mobility at lower temperatures. However, below the threshold voltage, the drain current decreases with a reduction in temperature. The relationship between the drain current and the gate voltage below the threshold voltage is expected to follow the Boltzmann limit. However, below 50 K, a deviation from this limit occurs, and subthreshold swing saturation becomes apparent. Additionally, the transconductance of the device exhibits a non-monotonic behavior, leading to an increase in the observed performance anomalies at low temperatures. Our proposed model captures the temperature-dependent effects in FETs observed from room temperature all the way down to cryogenic temperatures.\u003C/p>","2024-12-18T17:26:07.891Z","2025-05-16T14:13:39.212Z","2024-12-18T17:26:08.965Z","34",[942],{"id":199,"name":943,"committee":16,"position":16,"affiliation":944,"email":16,"biography":945,"createdAt":946,"updatedAt":947,"url_path_id":948,"contactPhoto":949,"socialLinks":982,"url_path":983},"Wajid Manzoor","IIT Kanpur","\u003Cp style=\"text-align:justify;\">Wajid Manzoor is a researcher at the NanoLab, Indian Institute of Technology (IIT) Kanpur, India. His work focuses on the characterization and modeling of MOSFETs at cryogenic temperatures, with the goal of advancing semiconductor technologies for low-temperature and quantum applications. He has published his research in IEEE and other reputed journals, contributing to the growing field of cryogenic electronics. \u003C/p>","2024-12-20T13:16:43.235Z","2025-05-29T20:12:29.258Z","37",{"id":950,"name":951,"alternativeText":16,"caption":16,"width":952,"height":953,"formats":954,"hash":978,"ext":341,"mime":344,"size":979,"url":980,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":981,"updatedAt":981},55,"1000033613.jpg",1824,3542,{"large":955,"small":961,"medium":967,"thumbnail":973},{"ext":341,"url":956,"hash":957,"mime":344,"name":958,"path":16,"size":959,"width":960,"height":347},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/large_1000033613_227bafdb13.jpg","large_1000033613_227bafdb13","large_1000033613.jpg",78.84,515,{"ext":341,"url":962,"hash":963,"mime":344,"name":964,"path":16,"size":965,"width":966,"height":354},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_1000033613_227bafdb13.jpg","small_1000033613_227bafdb13","small_1000033613.jpg",20.2,258,{"ext":341,"url":968,"hash":969,"mime":344,"name":970,"path":16,"size":971,"width":972,"height":361},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/medium_1000033613_227bafdb13.jpg","medium_1000033613_227bafdb13","medium_1000033613.jpg",44.26,386,{"ext":341,"url":974,"hash":975,"mime":344,"name":976,"path":16,"size":977,"width":702,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_1000033613_227bafdb13.jpg","thumbnail_1000033613_227bafdb13","thumbnail_1000033613.jpg",3.03,"1000033613_227bafdb13",1152.32,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/1000033613_227bafdb13.jpg","2025-05-29T20:12:26.765Z",[],"-21","-20",{"id":35,"session":986},{"id":35,"title":987,"teaser":67,"body":988,"createdAt":989,"updatedAt":990,"publishedAt":991,"url_path_id":992,"contacts":993,"url_path":1024},"Performance and Compact Modeling of Transistors for Wide Temperature Range Electronics","\u003Cp style=\"text-align:justify;\">There is currently renewed interest in cryo device operation driven by quantum computing (mK-4K), high-performance computing (<100K), and space exploration (e.g., 93-400K lunar day/night, 25K in dark polar craters).  This paper shares our experiences in cryo device performance characterization and compact modeling in enabling the design of circuits that can operate across a wide temperature range without using warm boxes.  Devices include FDSOI, LDMOS and SiGe HBTs of various breakdown voltages.\u003C/p>","2024-12-18T17:25:50.679Z","2025-05-05T15:55:41.517Z","2024-12-18T17:25:52.015Z","33",[994],{"id":121,"name":995,"committee":16,"position":16,"affiliation":996,"email":16,"biography":997,"createdAt":998,"updatedAt":999,"url_path_id":1000,"contactPhoto":1001,"socialLinks":1022,"url_path":1023},"Guofu Niu","Auburn University","\u003Cp style=\"text-align:justify;\">Dr. Guofu Niu is the Ed and Peggy Reynolds Family Professor at Auburn University. His research includes SiGe devices, RF CMOS, high-frequency characterization, noise, radiation effects, cryogenic electronics, compact modeling, and TCAD. Dr. Niu has published over 200 papers, and co-authored the book \"Silicon-Germanium Heterojunction Bipolar Transistors\". He served as an Editor for IEEE Transactions on Electron Devices and as chair or committee member for conferences including the IEEE SiRF, NSREC and BCTM.\u003C/p>","2024-12-18T17:23:47.723Z","2025-05-05T16:18:16.354Z","28",{"id":534,"name":1002,"alternativeText":16,"caption":16,"width":1003,"height":1004,"formats":1005,"hash":1018,"ext":341,"mime":344,"size":1019,"url":1020,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":1021,"updatedAt":1021},"For Guou Niu.jpg",532,595,{"small":1006,"thumbnail":1012},{"ext":341,"url":1007,"hash":1008,"mime":344,"name":1009,"path":16,"size":1010,"width":1011,"height":354},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_For_Guou_Niu_09f00ed6f5.jpg","small_For_Guou_Niu_09f00ed6f5","small_For Guou Niu.jpg",52.37,447,{"ext":341,"url":1013,"hash":1014,"mime":344,"name":1015,"path":16,"size":1016,"width":1017,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_For_Guou_Niu_09f00ed6f5.jpg","thumbnail_For_Guou_Niu_09f00ed6f5","thumbnail_For Guou Niu.jpg",7.49,140,"For_Guou_Niu_09f00ed6f5",71.26,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/For_Guou_Niu_09f00ed6f5.jpg","2025-05-05T16:18:14.210Z",[],"-14","-19",{"id":182,"session":1026},{"id":182,"title":1027,"teaser":67,"body":1028,"createdAt":1029,"updatedAt":1030,"publishedAt":1031,"url_path_id":1032,"contacts":1033,"url_path":1058},"The Family of MVSG Compact Models for High-voltage Gallium-Nitride Devices","\u003Cp style=\"text-align:justify;\">MIT Virtual-source Gallium-nitride (MVSG) FET compact model was first introduced as a physics-based compact model for radio-frequency (RF) GaN transistors in 2012, and later been selected as a CMC-approved industry standard GaN transistor model. With the rapid evolution and innovation in the field of GaN technology, continuous efforts have been made to improve, update and expand the capabilities of the MVSG models. This paper first provides an overview of the basics of the MVSG compact models. We will then introduce the variety of compact models in the MVSG family for GaN-based transistors, multi-channel diodes, and transmission-line resistors. With the accuracy, scalability and flexibility, the MVSG family of physics-based GaN device compact models provide a solid foundation for the development of Process Design Kit for HV GaN technology, and also serves as useful research vehicles to explore GaN-based device physics, device engineering, and circuit design.\u003C/p>","2024-12-20T13:17:41.694Z","2025-05-05T15:56:08.476Z","2024-12-20T13:17:43.065Z","38",[1034],{"id":243,"name":1035,"committee":16,"position":16,"affiliation":1036,"email":16,"biography":1037,"createdAt":1038,"updatedAt":1039,"url_path_id":1040,"contactPhoto":1041,"socialLinks":1056,"url_path":1057},"Lan Wei","University of Waterloo","\u003Cp style=\"text-align:justify;\">Prof. Lan Wei received her B.S. in Microelectronics from Peking University, China (2005), M.S and Ph. D. in Electrical Engineering from Stanford University, USA (2007 and 2010, respectively). She is currently an Associate Professor at the University of Waterloo, Canada. She has intensive experience in device physics-based compact modeling including silicon and GaN technologies, device-circuit interactive design and optimization, integrated nanoelectronic systems with low-dimensional materials, cryogenic CMOS device modeling and circuit design for quantum computing.  She has authored/co-authored more than 100 peered reviewed publications and served on the technical program committees including IEDM, ICCAD, DATE, VLSI-TSA, GLSVLSI, ISQED, BCICTS, ISPSD, EDTM, etc. \u003C/p>","2024-12-18T17:23:56.522Z","2025-05-05T15:53:26.889Z","29",{"id":1042,"name":1043,"alternativeText":16,"caption":16,"width":1044,"height":1045,"formats":1046,"hash":1053,"ext":20,"mime":23,"size":484,"url":1054,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":1055,"updatedAt":1055},45,"Picture1.png",228,264,{"thumbnail":1047},{"ext":20,"url":1048,"hash":1049,"mime":23,"name":1050,"path":16,"size":1051,"width":1052,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_Picture1_96eb0f16aa.png","thumbnail_Picture1_96eb0f16aa","thumbnail_Picture1.png",38.18,135,"Picture1_96eb0f16aa","https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/Picture1_96eb0f16aa.png","2025-05-05T15:52:47.202Z",[],"-15","-22",{"id":236,"session":1060},{"id":236,"title":1061,"teaser":67,"body":1062,"createdAt":1063,"updatedAt":1064,"publishedAt":1065,"url_path_id":1066,"contacts":1067,"url_path":1105},"Compact Modeling by HiSIM for High-Voltage Devices","\u003Cp style=\"text-align:justify;\">HiSIM_HV, a compact model for high-voltage MOSFET, has been widely used since its selection as a Compact Model Coalition (CMC) standard model, in 2007, and its first production release in 2008. Through the collaboration with CMC since then, HiSIM_HV has continued to expand its scope to meet the industry's increasing demands. In this paper, the modeling approach of HiSIM_HV is reviewed. The modeling concept was extended to other classes of high voltage devices such as IGBTs and Super-Junction MOSFETs, thanks to the flexibility in modeling by the potential-based modeling approach.\u003C/p>","2024-12-20T13:20:57.747Z","2025-06-16T22:18:06.904Z","2024-12-20T13:20:58.969Z","40",[1068],{"id":156,"name":1069,"committee":16,"position":16,"affiliation":1070,"email":16,"biography":1071,"createdAt":1072,"updatedAt":1073,"url_path_id":1074,"contactPhoto":1075,"socialLinks":1103,"url_path":1104},"Mitiko Miura-Mattausch","Graduate School of Advanced Sciences of Matter, Hiroshima University","\u003Cp style=\"text-align:justify;\">Mitiko Miura-Mattausch was a professor at the Graduate School of Advanced Sciences of Matter, Hiroshima University, leading the Ultra-Scaled-Devices Laboratory. As a professor emeritus she is now focusing on the support of the HiSIM research center.​\u003C/p>\u003Cp style=\"text-align:justify;\">In her presentation, she focuses on high-voltage MOSFETs modeling, where the structure-specific spatial distribution of the potential as well as of the current flow cannot be ignored. The model extensions to IGBT as well as SJ-MOSFET are demonstrated to secure accurate power-loss prediction.  ​\u003C/p>","2024-12-20T13:20:35.274Z","2025-05-07T23:36:31.456Z","39",{"id":1076,"name":1077,"alternativeText":16,"caption":16,"width":337,"height":338,"formats":1078,"hash":1099,"ext":341,"mime":344,"size":1100,"url":1101,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":1102,"updatedAt":1102},51,"icmc speaker.jpg",{"large":1079,"small":1084,"medium":1089,"thumbnail":1094},{"ext":341,"url":1080,"hash":1081,"mime":344,"name":1082,"path":16,"size":1083,"width":347,"height":348},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/large_icmc_speaker_36c10d315a.jpg","large_icmc_speaker_36c10d315a","large_icmc speaker.jpg",69.86,{"ext":341,"url":1085,"hash":1086,"mime":344,"name":1087,"path":16,"size":1088,"width":354,"height":355},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_icmc_speaker_36c10d315a.jpg","small_icmc_speaker_36c10d315a","small_icmc speaker.jpg",18.17,{"ext":341,"url":1090,"hash":1091,"mime":344,"name":1092,"path":16,"size":1093,"width":361,"height":362},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/medium_icmc_speaker_36c10d315a.jpg","medium_icmc_speaker_36c10d315a","medium_icmc speaker.jpg",39.72,{"ext":341,"url":1095,"hash":1096,"mime":344,"name":1097,"path":16,"size":1098,"width":368,"height":369},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_icmc_speaker_36c10d315a.jpg","thumbnail_icmc_speaker_36c10d315a","thumbnail_icmc speaker.jpg",5.38,"icmc_speaker_36c10d315a",109.98,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/icmc_speaker_36c10d315a.jpg","2025-05-07T23:36:03.589Z",[],"-23","-8",{"id":135,"session":1107},{"id":135,"title":1108,"teaser":67,"body":1109,"createdAt":1110,"updatedAt":1111,"publishedAt":1112,"url_path_id":1113,"contacts":1114,"url_path":1159},"Recent Topics in HBT Compact Modeling for RF Applications","\u003Cp style=\"text-align:justify;\">The most recent model extensions of the industry-standard hetero-junction bipolar transistor (HBT) compact model HICUM/L2 are discussed in view of its application for high-frequency (HF) circuit design. Possible issues that may require further development are pointed out. A concise overview of model usage examples in the design of a large variety of HF circuits is provided. Present research topics that will lead to future model extensions comprise (i) HBT reliability during large-signal radio-frequency (RF) operation, (ii) InP HBT related transport physics, and (iii) operation at cryogenic temperatures for qubit read-out circuits.\u003C/p>","2025-01-03T14:58:28.999Z","2025-05-05T15:56:58.692Z","2025-01-03T14:58:30.056Z","42",[1115],{"id":142,"name":1116,"committee":16,"position":16,"affiliation":1117,"email":16,"biography":1118,"createdAt":1119,"updatedAt":1120,"url_path_id":1121,"contactPhoto":1122,"socialLinks":1157,"url_path":1158},"Michael Schröter","TU Dresden","\u003Cp style=\"text-align:justify;\">Michael Schröter received his Dr.-Ing. degree (1988) and venia-legendi (1994) in electrical engineering from Ruhr-University Bochum, Germany. During eight years in industry, he held engineering and management positions at Nortel/BNR in Ottawa, Canada, and at Rockwell/Conexant and RFNano in Newport Beach (CA), USA. Since 1999, he has been a Full Professor at Technical University Dresden, Germany. He was the initiator and Technical Project Manager for the EU projects DOTFIVE and DOTSEVEN that led to SiGe HBT technologies with world-record performance. He is the author of the industry standard compact bipolar transistor model HICUM, and his team created the ITRS/IRDS data for SiGe HBTs. From 2013 to 2019, he led the carbon nanotube transistor development of the German Excellence Cluster “Center for Advancing Electronics Dresden”. He is also a co-founder of XMOD Technologies in Bordeaux, France, and Semimod GmbH in Dresden, Germany.\u003C/p>","2025-01-03T14:58:01.112Z","2025-05-05T16:15:45.167Z","41",{"id":1123,"name":1124,"alternativeText":16,"caption":16,"width":1125,"height":1126,"formats":1127,"hash":1152,"ext":341,"mime":344,"size":1153,"url":1154,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":1155,"updatedAt":1156},49,"Michael Schroter.jpg",1088,1486,{"large":1128,"small":1134,"medium":1140,"thumbnail":1146},{"ext":341,"url":1129,"hash":1130,"mime":344,"name":1131,"path":16,"size":1132,"width":1133,"height":347},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/large_Michael_Schroter_18f9b75b9a.jpg","large_Michael_Schroter_18f9b75b9a","large_Michael Schroter.jpg",107.31,732,{"ext":341,"url":1135,"hash":1136,"mime":344,"name":1137,"path":16,"size":1138,"width":1139,"height":354},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_Michael_Schroter_18f9b75b9a.jpg","small_Michael_Schroter_18f9b75b9a","small_Michael Schroter.jpg",27.26,366,{"ext":341,"url":1141,"hash":1142,"mime":344,"name":1143,"path":16,"size":1144,"width":1145,"height":361},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/medium_Michael_Schroter_18f9b75b9a.jpg","medium_Michael_Schroter_18f9b75b9a","medium_Michael Schroter.jpg",60.98,549,{"ext":341,"url":1147,"hash":1148,"mime":344,"name":1149,"path":16,"size":1150,"width":1151,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_Michael_Schroter_18f9b75b9a.jpg","thumbnail_Michael_Schroter_18f9b75b9a","thumbnail_Michael Schroter.jpg",3.77,115,"Michael_Schroter_18f9b75b9a",153.03,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/Michael_Schroter_18f9b75b9a.jpg","2025-05-05T16:14:17.306Z","2025-05-05T16:15:41.643Z",[],"-25","-26",{"id":263,"session":1161},{"id":263,"title":1162,"teaser":67,"body":1163,"createdAt":1164,"updatedAt":1165,"publishedAt":1166,"url_path_id":1167,"contacts":1168,"url_path":1192},"Overview of L-UTSOI, a Standard Compact Model for FD-SOI Technologies","\u003Cp style=\"text-align:justify;\">Fully-Depleted Silicon-On-Insulator (FD-SOI) technologies featuring Ultra-Thin silicon Body and Buried (UTBB) oxide are now widely used for cost and power sensitive applications and also promising candidates for the next generations of chips. In particular, the interest of back-bias control for power management requires an accurate compact model capable of capturing all related physical features. Several SPICE models have been developed to account for the specific characteristics of FD-SOI transistors. In this context, L-UTSOI was the first available standard compact model to account for the strong inversion at the back interface. This model, based on an innovative explicit solution to compute the surface potentials at front and back interfaces under all operating conditions, has been enriched over the years with features that physically and accurately describe the behavior of FD-SOI transistors up to RF frequencies and down to cryogenic temperatures.\u003C/p>","2025-01-13T13:33:23.105Z","2025-05-05T15:57:24.657Z","2025-01-13T13:33:24.250Z","45",[1169],{"id":93,"name":1170,"committee":16,"position":16,"affiliation":1171,"email":16,"biography":1172,"createdAt":1173,"updatedAt":1174,"url_path_id":1175,"contactPhoto":1176,"socialLinks":1190,"url_path":1191},"Thierry Poiroux","CEA-Leti","\u003Cp style=\"text-align:justify;\">Thierry Poiroux received the M.S. degree from Ecole Centrale Paris, France, in 1995 and the Ph.D. degree from the University of Nantes, France, in 2000. After a Ph.D. work carried out at the Commissariat à l’Énergie Atomique/Laboratoire d’Electronique et de Technologie de l’Information (CEA–Leti), Grenoble, France, and Matra MHS on plasma process-induced damage, he joined CEA–Leti as a Research Staff Member in 2000. Until 2002, he was involved in partially and fully depleted silicon-on-insulator (SOI) process integration and compact modeling. From 2002 to 2010, he worked on advanced device architectures and was in charge of multiple-gate device modeling, planar double gate process integration and fabrication of graphene-based transistors. In 2011 and 2012, he has been the Head of the Innovative Device Laboratory of CEA–Leti, dedicated to the development of advanced CMOS technologies. From 2012 to 2018, he developed the second version of the L–UTSOI compact model, selected by the Si2 Compact Model Coalition as a standard industrial model for fully-depleted SOI technologies. From 2018 to 2021, he was the head of the Simulation and Compact Model Laboratory of CEA–Leti. From 2021 to March 2025, he was in charge of the Characterization, Design and Simulation Department, and he is currently project leader. He has authored or coauthored five book chapters and about 190 papers and communications, and he is author or co-author of about 20 patents.\u003C/p>","2025-01-13T13:32:49.762Z","2025-05-05T16:16:21.755Z","43",{"id":1177,"name":1178,"alternativeText":16,"caption":16,"width":566,"height":1044,"formats":1179,"hash":1186,"ext":20,"mime":23,"size":1187,"url":1188,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":1189,"updatedAt":1189},46,"Thierry Poiroux.png",{"thumbnail":1180},{"ext":20,"url":1181,"hash":1182,"mime":23,"name":1183,"path":16,"size":1184,"width":1185,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_Thierry_Poiroux_169768ba33.png","thumbnail_Thierry_Poiroux_169768ba33","thumbnail_Thierry Poiroux.png",40.53,137,"Thierry_Poiroux_169768ba33",24.78,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/Thierry_Poiroux_169768ba33.png","2025-05-05T16:14:16.920Z",[],"-27","-29",{"id":199,"session":1194},{"id":243,"title":1195,"teaser":67,"body":1196,"createdAt":1197,"updatedAt":1198,"publishedAt":1199,"url_path_id":1200,"contacts":1201,"url_path":1228},"Breakdown and C-V Characteristics Analysis of Depletion Mode Lateral β-Ga2O3 MOSFET","\u003Cp style=\"text-align:justify;\">Gallium oxide (Ga2O3) has recently become a highly intriguing semiconductor, particularly in the field of power electronics. Ultra-wide bandgap (~5 eV) and higher dielectric constant (~10.5-12.5) are the two properties far better than silicon carbide (SiC) and gallium nitride (GaN). β-Ga2O3 is the most stable phase among the five polymorphs (α, β, γ, δ, and ϵ). Moreover, a key advantage of β-Ga2O3 over SiC and GaN is its ability to produce high-quality native crystals at a lower cost. Devices based on β-Ga2O3, such as Schottky barrier diodes and depletion-mode lateral MOSFETs, have demonstrated stable I-V characteristics at voltages exceeding 1 kV. However, limited research has been conducted on the capacitance-voltage (C-V) analysis of β-Ga2O3 devices. This paper presents a TCAD simulation of a β-Ga2O3 depletion-mode lateral MOSFET (D-MOSFET), which exhibits stable characteristics up to 370V. The reverse transfer capacitance (Crss), output capacitance (Coss), and input capacitance (Ciss) of the device were analyzed using Silvaco. The lower capacitances are expected because of the higher dielectric constant of β-Ga2O3. Additionally, the electron concentration distribution was studied to illustrate the expansion of the depletion region with increasing drain voltage. These findings provide valuable insights for future modeling and optimization of β-Ga2O3 depletion-mode lateral MOSFETs.\u003C/p>","2025-01-24T16:20:04.799Z","2025-05-05T15:57:52.846Z","2025-01-24T16:20:06.194Z","49",[1202],{"id":249,"name":1203,"committee":16,"position":16,"affiliation":1204,"email":16,"biography":1205,"createdAt":1206,"updatedAt":1207,"url_path_id":1208,"contactPhoto":1209,"socialLinks":1226,"url_path":1227},"Alan Mantooth","Distinguished Professor Arkansas University and IEEE Board Director","\u003Cp style=\"text-align:justify;\">Alan Mantooth received the B.S.E.E. and M.S.E.E. degrees from the University of Arkansas in 1985 and 1986, and the Ph.D. degree from Georgia Tech in 1990. He then joined Analogy, a startup company in Oregon. In 1998, he joined the faculty of the Department of Electrical Engineering at the University of Arkansas, Fayetteville, where he currently holds the rank of Distinguished Professor. His research interests now include analog and mixed-signal IC design & CAD, semiconductor device modeling, power electronics, power electronic packaging, and cybersecurity. Dr. Mantooth established and serves as Executive Director of the National Center for Reliable Electric Power Transmission (NCREPT). Professor Mantooth is the Founding Director of the NSF Industry/University Cooperative Research Center on GRid-connected Advanced Power Electronic Systems (GRAPES) and Deputy Director of the POETS NSF Engineering Research Center. Dr. Mantooth holds the 21st Century Research Leadership Chair in Engineering. He is a Past-President of the IEEE Power Electronics Society. He currently serves the profession as Editor-in-Chief of the IEEE Open Journal of Power Electronics and as Division II Director of IEEE. Dr. Mantooth is a Fellow of IEEE, a member of Tau Beta Pi, Sigma Xi, and Eta Kappa Nu, and registered professional engineer in Arkansas.\u003C/p>","2025-01-13T19:38:08.940Z","2025-06-18T21:52:36.237Z","47",{"id":1210,"name":1211,"alternativeText":16,"caption":16,"width":338,"height":338,"formats":1212,"hash":1222,"ext":341,"mime":344,"size":1223,"url":1224,"previewUrl":16,"provider":30,"provider_metadata":16,"createdAt":1225,"updatedAt":1225},60,"Alan Montooth.jpg",{"small":1213,"thumbnail":1217},{"ext":341,"url":1214,"hash":1215,"mime":344,"name":1216,"path":16,"size":25,"width":354,"height":354},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/small_Alan_Montooth_fb1ffdf749.jpg","small_Alan_Montooth_fb1ffdf749","small_Alan Montooth.jpg",{"ext":341,"url":1218,"hash":1219,"mime":344,"name":1220,"path":16,"size":1221,"width":26,"height":26},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/thumbnail_Alan_Montooth_fb1ffdf749.jpg","thumbnail_Alan_Montooth_fb1ffdf749","thumbnail_Alan Montooth.jpg",4.56,"Alan_Montooth_fb1ffdf749",59.8,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/si225/Alan_Montooth_fb1ffdf749.jpg","2025-06-18T21:52:34.019Z",[],"-31","-33",{"data":1230,"meta":1231},{"id":93,"heading":264,"createdAt":269,"updatedAt":270,"publishedAt":271,"url_path_id":272,"url_path":275,"contentType":105},{},1778853476998]