Speakers

Compact modeling is hard: It is easy to make mistakes in the formulation of a model, in the implementation of a model, and in parameter extraction for a model. This talk will discuss how the adoption of Verilog-A, the evolution of benchmark tests (unfortunately primarily only for MOS transistor modeling), the CMC requirement for standard models to include QA (quality assurance) tests and “golden” reference results, and VAMPyRE, have all helped elevate the baseline “health” of compact models. There are still many challenges. Models continue to be released with numerical issues and parameter extraction procedures can still give values that cause unphysical behavior. At present, we rely on non-artificial intelligence (“institutional knowledge”) to try, unsuccessfully, to prevent such problems from recurring. This talk will show how some numerical issues can be (manually) detected and resolved, review benchmarks for AI/ML compact models and parameter extraction, and speculate on avenues for future improvements.

Dr. Green will reflect on the early days of the CMC, from its origin as a Sematech Workshop in 1995 to its rapid establishment as the premier, international modeling standards organization. He will share some of the challenges and accomplishments that were part of the journey, and he will highlight aspects of the CMC that make it a special and unique community for its members.

Looking forward, Dr. Green will present some interesting technical challenges the CMC might want to consider for future standards. These are potential opportunities for the CMC to expand its portfolio, its membership and its influence. Specifically, three areas will be discussed: mechanical stress effects in semiconductor devices (e.g., due to chip-package interactions), the impact of X-Ray radiation, and integrated sensors. 

‘Neural networks have taken the world by storm’ -- the saying goes currently. Neural network models are finding new applications every day, upending conventional workflow and ushering unprecedented productivity. Will they also power the next generation compact models? In this presentation, I will examine this possibility with some concrete examples. In essence, neural networks could learn patterns from same type of calculations, potentially providing results without having to go through those same calculation steps again and again. If this can indeed be achieved, it should substantially improve the speed of execution. Based on the recent work in the BSIM group, I shall discuss how neural networks perform in the context of reproducing conventional device level parameters such as current, voltage, noise etc. as well how it behaves in prototypical circuit simulation. Model development, usage of parameters and acceleration behavior will be presented. I shall also discuss potential outlook for such Neural Network enhanced compact models for advanced technology simulation.

This article explores a detailed analysis of an industry-standard model optimized for temperature scalability, ranging from room temperature to cryogenic temperatures. As the fundamental device physics of silicon is temperature-dependent, therefore, the electrical characteristics of field effect transistors (FETs) also exhibit noticeable changes with varying temperatures. One of the most prominent observations is the significant increase in the drain current as temperature decreases. This increase is primarily attributed to enhanced carrier mobility at lower temperatures. However, below the threshold voltage, the drain current decreases with a reduction in temperature. The relationship between the drain current and the gate voltage below the threshold voltage is expected to follow the Boltzmann limit. However, below 50 K, a deviation from this limit occurs, and subthreshold swing saturation becomes apparent. Additionally, the transconductance of the device exhibits a non-monotonic behavior, leading to an increase in the observed performance anomalies at low temperatures. Our proposed model captures the temperature-dependent effects in FETs observed from room temperature all the way down to cryogenic temperatures.

There is currently renewed interest in cryo device operation driven by quantum computing (mK-4K), high-performance computing (<100K), and space exploration (e.g., 93-400K lunar day/night, 25K in dark polar craters).  This paper shares our experiences in cryo device performance characterization and compact modeling in enabling the design of circuits that can operate across a wide temperature range without using warm boxes.  Devices include FDSOI, LDMOS and SiGe HBTs of various breakdown voltages.

MIT Virtual-source Gallium-nitride (MVSG) FET compact model was first introduced as a physics-based compact model for radio-frequency (RF) GaN transistors in 2012, and later been selected as a CMC-approved industry standard GaN transistor model. With the rapid evolution and innovation in the field of GaN technology, continuous efforts have been made to improve, update and expand the capabilities of the MVSG models. This paper first provides an overview of the basics of the MVSG compact models. We will then introduce the variety of compact models in the MVSG family for GaN-based transistors, multi-channel diodes, and transmission-line resistors. With the accuracy, scalability and flexibility, the MVSG family of physics-based GaN device compact models provide a solid foundation for the development of Process Design Kit for HV GaN technology, and also serves as useful research vehicles to explore GaN-based device physics, device engineering, and circuit design.

HiSIM_HV, a compact model for high-voltage MOSFET, has been widely used since its selection as a Compact Model Coalition (CMC) standard model, in 2007, and its first production release in 2008. Through the collaboration with CMC since then, HiSIM_HV has continued to expand its scope to meet the industry's increasing demands. In this paper, the modeling approach of HiSIM_HV is reviewed. The modeling concept was extended to other classes of high voltage devices such as IGBTs and Super-Junction MOSFETs, thanks to the flexibility in modeling by the potential-based modeling approach.

The most recent model extensions of the industry-standard hetero-junction bipolar transistor (HBT) compact model HICUM/L2 are discussed in view of its application for high-frequency (HF) circuit design. Possible issues that may require further development are pointed out. A concise overview of model usage examples in the design of a large variety of HF circuits is provided. Present research topics that will lead to future model extensions comprise (i) HBT reliability during large-signal radio-frequency (RF) operation, (ii) InP HBT related transport physics, and (iii) operation at cryogenic temperatures for qubit read-out circuits.

Fully-Depleted Silicon-On-Insulator (FD-SOI) technologies featuring Ultra-Thin silicon Body and Buried (UTBB) oxide are now widely used for cost and power sensitive applications and also promising candidates for the next generations of chips. In particular, the interest of back-bias control for power management requires an accurate compact model capable of capturing all related physical features. Several SPICE models have been developed to account for the specific characteristics of FD-SOI transistors. In this context, L-UTSOI was the first available standard compact model to account for the strong inversion at the back interface. This model, based on an innovative explicit solution to compute the surface potentials at front and back interfaces under all operating conditions, has been enriched over the years with features that physically and accurately describe the behavior of FD-SOI transistors up to RF frequencies and down to cryogenic temperatures.

Gallium oxide (Ga2O3) has recently become a highly intriguing semiconductor, particularly in the field of power electronics. Ultra-wide bandgap (~5 eV) and higher dielectric constant (~10.5-12.5) are the two properties far better than silicon carbide (SiC) and gallium nitride (GaN). β-Ga2O3 is the most stable phase among the five polymorphs (α, β, γ, δ, and ϵ). Moreover, a key advantage of β-Ga2O3 over SiC and GaN is its ability to produce high-quality native crystals at a lower cost. Devices based on β-Ga2O3, such as Schottky barrier diodes and depletion-mode lateral MOSFETs, have demonstrated stable I-V characteristics at voltages exceeding 1 kV. However, limited research has been conducted on the capacitance-voltage (C-V) analysis of β-Ga2O3 devices. This paper presents a TCAD simulation of a β-Ga2O3 depletion-mode lateral MOSFET (D-MOSFET), which exhibits stable characteristics up to 370V. The reverse transfer capacitance (Crss), output capacitance (Coss), and input capacitance (Ciss) of the device were analyzed using Silvaco. The lower capacitances are expected because of the higher dielectric constant of β-Ga2O3. Additionally, the electron concentration distribution was studied to illustrate the expansion of the depletion region with increasing drain voltage. These findings provide valuable insights for future modeling and optimization of β-Ga2O3 depletion-mode lateral MOSFETs.